The invention addresses the task of providing a memory arrangement which enables data packets to be written to or read from at least one memory area connected to two memory-accessing units in a consistent and especially conflict-free manner both in the case of a write access of a memory-accessing unit and in the case of a read access of another memory-accessing unit.
According to the invention, this object is achieved by the electronic memory arrangement in accordance with this invention.
The at least three memory areas are preferably part of a common physical memory unit or alternatively preferably in each case arranged in a separate physical memory unit.
The memory control unit is preferably designed in such a manner that after the writing of a data packet to one of the three memory areas, the subsequent data packet to be written is written to one of the other memory areas.
The at least two memory-accessing units are preferably constructed as separate electronic units and in this context especially one as a sensor and an evaluating circuit, and the other one as electronic control unit, especially preferably of a motor vehicle control system. In this context, it is appropriate that the memory control unit, the at least three memory areas and the multiplexer units are also arranged in this electronic control unit.
A data packet or defined data packet, respectively, includes preferably a number of data words (bytes). In particular, a data word comprises a defined number of bits, for example 8 bits or 16 bits. The size and/or structure of data packets and/or data words can differ with respect to the different memory-accessing units.
The memory control unit is preferably designed in such a manner that successive data packets to be written are written alternately to two of the three memory areas as long as there is no read access to one of these two memory areas.
It is preferred that the memory arrangement is constructed as a data buffer which enables one of the memory-accessing units to be provided with a data packet at any time per read access wherein the other memory-accessing unit can write data packets successively in each case to one of the memory areas, wherein the respective selection of the memory area to which a write access is taking place is performed by the memory control unit.
The memory arrangement is preferably constructed as data transmission channel between the at least two memory-accessing units, wherein the data transmission channel comprises the at least three memory areas and the memory accesses which are controlled by the memory control unit.
It is preferred that the at least three memory areas are connected at the input end and/or the output end via a, especially in each case one, multiplexer unit which is/are controlled by the memory control unit for assigning a read or write access of the memory-accessing units to one of the three memory areas.
The memory arrangement is preferably connected at the input end to the electronic evaluating circuit of a sensor element as at least writing memory-accessing unit, wherein the electronic evaluating circuit of the sensor element successively continuously provides, and writes into the memory arrangement, new data packets.
It is appropriate that the memory control unit is constructed in such a manner that it displays a defined address area only once towards the outside, that is to say with respect to the memory-accessing units, wherein the memory-accessing units and especially other external units address this address area only once and not its triple realization in the three memory areas. In this context, the address area externally visible or addressable is especially preferably as large as the internal address area of each of the at least three memory areas individually.
It is preferred that the memory control unit is constructed in such a manner that in the case of the presence of a data request signal, the read access is carried out to the last memory area written to, wherein the writing of a data packet performed last must have been concluded.
It is expedient that the memory arrangement is constructed in accordance with a selecting-reading “sample mode”, wherein, after the transmission of a data freeze signal by a reading memory-accessing unit to the memory control unit, data are preserved in one of the memory areas in unchanged form for a defined period, for example until they are actually read out, whereupon the further write access to the memory area last written to, wherein this write access must be concluded, is prevented and/or blocked by the memory control unit until the desired data have been read out of this memory area at a later time or until a new data freeze signal is sent by the reading memory-accessing unit.
It is preferred that the memory arrangement additionally has a control read unit which is connected to each of the three memory areas, especially by means of a multiplexer, and the memory control unit and wherein the control read unit is designed in such a manner and activated in such a manner that in each case after a write process, the data packet written last is directly read out again and subsequently compared again with the data packet to be written lastly in order to detect one or more possible write errors, wherein the complete write access is ended only after the repeated reading-out and successful comparison by the control read unit. In particular, the memory arrangement is constructed in such a manner that after an unsuccessful comparison, that is to say data packets compared differ, the write process is repeated and/or a write error is signaled or noted electronically.
The data request signal and/or the data freeze signal is preferably replaced by a read access to a defined memory address.
It is preferred that the writing memory-accessing unit provides a signal with the information that a data packet has been written completely, as part of a write access, to the memory control unit.
It is expedient that the reading memory-accessing unit provides a signal with the information that a data packet has been read completely, as part of a read access, to the memory control unit.
The invention also relates to the use of the memory arrangement in motor vehicles, especially in an electronic control unit of a motor vehicle control system.
The three memory areas are preferably essentially constructed to be equal and have in each case the identical memory volume or address volume.
A multiplexer unit is preferably understood to be a multiplexer or a demultiplexer.
At the output end, the memory arrangement is connected preferably directly or indirectly to a memory-accessing unit and constructed as electronic control unit which successively reads particular data packets out of the memory arrangement.
The memory arrangement comprises especially more than three memory areas, for example redundant memory areas in order to increase the fault tolerance.
The information that data or data packets have been written or read completely as part of a write access or read access, or that the write access is ended, is preferably conveyed by the fact that this information is written to/into a defined address.